1. Field of the Invention
This invention relates to the fabrication of integrated circuit devices and more particularly to a method of fabricating high density dynamic random access memory (DRAM) devices which feature a new capacitor structure.
2. Description of the Prior Art
As DRAMs are scaled down in dimensions, there is a continuous challenge to maintain a sufficiently high stored charge per capacitor unit area. In order to construct high density DRAMs in a reasonable sized chip area, the cell structures have to change from the conventional planar-type capacitors to either trench capacitors or stack capacitors, in particular beyond the 4 Mbit DRAM era. All efforts to increase capacitance without increasing the planar area of the capacitor can be categorized into the following techniques:
(1) Thinning the capacitor dielectric and/or using films with a higher dielectric constant, such as oxide-nitride-oxide (ONO) films composite, and more recently tantalum pentoxide which will require further development to overcome leakage and reliability problems. PA1 (2) Building three dimensional capacitor structures to increase the capacitor area without increasing the planar area of the capacitor. There are two major branches of this approach, that is trench capacitors and stacked capacitors. In the category of trench capacitors, when the DRAM is beyond 16 Mbit, the trench needs to be very deep. There are technology and even theoretical physical limitations to processing the deep trenches that would be needed. When the stacked capacitor approach is used to fabricate 16 Mbit DRAMs and beyond, very complicated stacked structures are needed, such as fin structures, crown structures, and so forth. The making of such structures require complicated manufacturing processes which are costly and result in reduced yield.
Most recently a new concept has been advanced which calls for roughening the polycrystalline silicon surface of the capacitor electrode to increase the surface area. Several techniques for achieving a roughened surface of a polycrystalline silicon electrode layer have been suggested in technical paper recently presented by M. Sakao et al entitled "A CAPACITOR-OVER-BIT-LINE (COB) CELL WITH A HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs" in IEDM 1990 TECHNICAL DIGEST pages 655-658; M. Yoshimaru et al entitled "RUGGED SURFACE POLY-SI ELECTRODE AND LOW TEMPERATURE DEPOSITED SILICON NITRIDE FOR 64 MBIT AND BEYOND STC DRAM CELL" in IEDM 1990 TECHNICAL DIGEST pages 659-662; Pierre C. Fazan et al entitled "ELECTRICAL CHARACTERIZATION OF TEXTURED INTERPOLY CAPACITORS FOR ADVANCED STACKED DRAMs" in IEDM 1990 TECHNICAL DIGEST pages 663-666; and R. Lee et al U.S. Pat. No. 5,037,773.
These techniques cited in the above paragraph have small process window and are difficult to control in a manufacturing environment.
A U.S. Pat. No. 5,110,752 filed 07/10/91 by the author of the present Patent Application, C. Y. Lu and entitled "Roughened Polysilicon Surface Capacitor Electrode Plate for High Density DRAM" describes a new method and resulting device for making a capacitor structure which has increased capacitance through roughening by a metal silicide preferential growth at the grain boundaries of the first polysilicon layer and then the removal of the metal silicide.